LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 652

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.3.3.2 Register with optional shift
34.2.3.4 Shift Operations
Remark: In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS,
BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater
than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
Instruction substitution:
instruction in cases where you specify a constant that is not permitted. For example, an
assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent
instruction CMN Rd, #0x2.
You specify an Operand2 register in the form:
Rm {, shift}
where:
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value
is used by the instruction. However, the contents in the register Rm remains unchanged.
Specifying a register with shift also updates the carry flag when used with certain
instructions. For information on the shift operations and how they affect the carry flag, see
Section 34.2.3.4 “Shift Operations”
Register shift operations move the bits in a register left or right by a specified number of
bits, the shift length. Register shift can be performed:
•
•
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm. It can be one of:
ASR#n: arithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL#n: logical shift left n bits, 1 ≤ n ≤ 31.
LSR#n: logical shift right n bits, 1 ≤ n ≤ 32.
ROR#n: rotate right n bits, 1 ≤ n ≤ 31.
RRX: rotate right one bit, with extend.
directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a
destination register
during the calculation of Operand2 by the instructions that specify the second
operand as a register with shift, see
instruction.
—: if omitted, no shift occurs, equivalent to LSL#0.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Your assembler might be able to produce an equivalent
Section
Chapter 34: Appendix: Cortex-M3 user guide
34.2.3.3. The result is used by the
UM10360
© NXP B.V. 2010. All rights reserved.
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