LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 48

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 10. PLL1 block diagram
4.6.2 PLL1 Control register (PLL1CON - 0x400F C0A0)
PLL input
clock
Table 29.
[1]
The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1
allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting PLL1 causes the USB subsystem to run from the PLL1 output clock. Changes
to the PLL1CON register do not take effect until a correct PLL feed sequence has been
given (see
Name
PLL1CFG
PLL1STAT
PLL1FEED
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
PLLSTAT[4:0]
PLLSTAT[10]
Divide by M
Detector
PLOCK
Phase
MSEL
PLL1 registers
Section 4.6.6
Description
PLL1 Configuration Register. Holding register
for updating PLL1 configuration values. Values
written to this register do not take effect until a
valid PLL1 feed sequence has taken place.
PLL1 Status Register. Read-back register for
PLL1 control and configuration information. If
PLL1CON or PLL1CFG have been written to,
but a PLL1 feed sequence has not yet occurred,
they will not reflect the current PLL1 state.
Reading this register provides the actual values
controlling PLL1, as well as PLL1 status.
PLL1 Feed Register. This register enables
loading of PLL1 control and configuration
information from the PLL1CON and PLL1CFG
registers into the shadow registers that actually
affect PLL1 operation.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
and
Controlled
Oscillator
Current-
Section
4.6.3).
Chapter 4: LPC17xx Clocking and power control
Fcco
PLLSTAT[6:5]
Divide by 2P
PSEL
Access Reset
R/W
RO
WO
PLL output
clock
100416
value
0
0
NA
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
Address
0x400F C0A4
0x400F C0A8
0x400F C0AC
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