LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 539

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
25.8.2 Shadow registers and simultaneous updates
25.8.3 Fast Abort (ABORT)
25.8.4 Capture events
The Limit, Match, and Commutation Pattern registers (MCLIM, MCMAT, and MCCP) are
implemented as register pairs, each consisting of a write register and an operational
register. Software writes into the write registers. The operational registers control the
actual operation of each channel and are loaded with the current value in the write
registers when the TC starts counting up from 0.
Updating of the functional registers can be disabled by setting a channel’s DISUP bit in
the MCCON register. If the DISUP bits are set, the functional registers are not updated
until software stops the channel.
If a channel is not running when software writes to its LIM or MAT register, the functional
register is updated immediately.
Software can write to a TC register only when its channel is stopped.
The MCPWM has an external input MCABORT. When this input goes low, all six MCO
outputs assume their “A passive” states, and the Abort interrupt is generated if enabled.
The outputs remain locked in “A passive” state until the ABORT interrupt flag is cleared or
the Abort interrupt is disabled. The ABORT flag may not be cleared before the MCABORT
input goes high.
In order to clear an ABORT flag, a 1 must be written to bit 15 of the MCINTF_CLR
register. This will remove the interrupt request. The interrupt can also be disabled by
writing a 1 to bit 15 of the MCINTEN_CLR register.
Each PWM channel can take a snapshot of its TC when an input signal transitions. Any
channel may use any combination of rising and/or falling edges on any or all of the MCI0-2
inputs as a capture event, under control of the MCCAPCON register. Rising or falling
edges on the inputs are detected synchronously with respect to PCLK.
Fig 125. Center-aligned waveform with dead time, POLA = 0
MCOB
MCOA
All information provided in this document is subject to legal disclaimers.
0
active
passive
Rev. 2 — 19 August 2010
MAT
DT
active
passive
LIM
MAT
Chapter 25: LPC17xx Motor control PWM
DT
passive
active
0
LIM
passive
UM10360
DT
© NXP B.V. 2010. All rights reserved.
active
POLA = 0
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