LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 660
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.4 Memory access instructions
Table 616
Table 616. Memory access instructions
Mnemonic
ADR
CLREX
LDM{mode}
LDR{type}
LDR{type}
LDR{type}T
LDR
LDREX{type}
POP
PUSH
STM{mode}
STR{type}
STR{type}
STR{type}T
STREX{type}
shows the memory access instructions:
All information provided in this document is subject to legal disclaimers.
Brief description
Load PC-relative address
Clear Exclusive
Load Multiple registers
Load Register using immediate offset
Load Register using register offset
Load Register with unprivileged access
Load Register using PC-relative address
Load Register Exclusive
Pop registers from stack
Push registers onto stack
Store Multiple registers
Store Register using immediate offset
Store Register using register offset
Store Register with unprivileged access
Store Register Exclusive
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
See
Section 34.2.4.1
Section 34.2.4.9
Section 34.2.4.6
Section 34.2.4.2
Section 34.2.4.3
Section 34.2.4.4
Section 34.2.4.5
Section 34.2.4.8
Section 34.2.4.7
Section 34.2.4.7
Section 34.2.4.6
Section 34.2.4.2
Section 34.2.4.3
Section 34.2.4.4
Section 34.2.4.8
UM10360
© NXP B.V. 2010. All rights reserved.
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