LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 237

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 225. USB DMA Request Set register (USBDMARSet - address 0x5000 C258) bit description
Table 226. USB UDCA Head register (USBUDCAH - address 0x5000 C280) bit description
Table 227. USB EP DMA Status register (USBEpDMASt - address 0x5000 C284) bit description
UM10360
User manual
Bit
0
1
31:2
Bit
6:0
31:7
Bit
0
1
31:2
EPxx_DMA_ENABLE
Symbol Value
EP0
EP1
EPxx
Symbol
-
UDCA_ADDR
Symbol
EP0_DMA_ENABLE
EP1_DMA_ENABLE
11.10.7.4 USB UDCA Head register (USBUDCAH - 0x5000 C280)
11.10.7.5 USB EP DMA Status register (USBEpDMASt - 0x5000 C284)
0
0
0
1
This register allows software to raise a DMA request. This can be useful when switching
from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA
mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is
not raised by hardware. Software can then use this register to manually start the DMA
transfer.
Software can also use this register to initiate a DMA transfer to proactively fill an IN
endpoint buffer before an IN token packet is received from the host.
USBDMARSet is a write-only register.
The USBDMARSet bit allocation is identical to the USBDMARSt register
The UDCA (USB Device Communication Area) Head register maintains the address
where the UDCA is located in the RAM. Refer to
communication area”
UDCA and DMA descriptors. USBUDCAH is a read/write register.
Bits in this register indicate whether DMA operation is enabled for the corresponding
endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set in
this register. USBEpDMASt is a read-only register.
Description
Reserved. Software should not write ones to reserved bits. The UDCA is aligned to
128-byte boundaries.
Start address of the UDCA.
Description
Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit
must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must
be 0).
Set the endpoint xx (2 ≤ xx ≤ 31) DMA request.
No effect.
Set the corresponding bit in USBDMARSt.
Value
0
0
0
1
Description
Control endpoint OUT (DMA cannot be enabled for this endpoint and
the EP0_DMA_ENABLE bit must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and
the EP1_DMA_ENABLE bit must be 0).
endpoint xx (2 ≤ xx ≤ 31) DMA enabled bit.
The DMA for endpoint EPxx is disabled.
The DMA for endpoint EPxx is enabled.
All information provided in this document is subject to legal disclaimers.
and
Rev. 2 — 19 August 2010
Section 11.15.4 “The DMA descriptor”
Chapter 11: LPC17xx USB device controller
Section 11.15.2 “USB device
for more details on the
UM10360
© NXP B.V. 2010. All rights reserved.
(Table
Reset value
0x00
0
0
0
Reset value
0
Reset value
0
0
0
222).
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