LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 781

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.3.12 Hard Fault Status Register
34.4.3.13 Memory Management Fault Address Register
34.4.3.14 Bus Fault Address Register
The HFSR gives information about events that activate the hard fault handler. See the
register summary in
This register is read, write to clear. This means that bits in the register read normally, but
writing 1 to any bit clears that bit to 0. The bit assignments are shown in
Table 671. HFSR bit assignments
Remark: The HFSR bits are sticky. This means as one or more fault occurs, the
associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit,
or by a reset.
The MMFAR contains the address of the location that generated a memory management
fault. See the register summary in
Table 672. MMFAR bit assignments
When an unaligned access faults, the address is the actual address that faulted. Because
a single read or write instruction can be split into multiple aligned accesses, the fault
address can be any address in the range of the requested access size.
Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR
is valid. See
The BFAR contains the address of the location that generated a bus fault. See the register
summary in
Bits
[31]
[30]
[29:2]
[1]
[0]
Bits
[31:0]
Name
DEBUGEVT
FORCED
-
VECTTBL
-
Name
ADDRESS
Table 654
Table
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668.
Table 654
Function
Reserved for Debug use. When writing to the register you must write 0 to
this bit, otherwise behavior is Unpredictable.
Indicates a forced hard fault, generated by escalation of a fault with
configurable priority that cannot be handles, either because of priority or
because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault
status registers to find the cause of the fault.
Reserved.
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return
points to the instruction that was preempted by the exception.
Reserved.
Function
When the MMARVALID bit of the MMFSR is set to 1, this field holds the
address of the location that generated the memory management fault
Rev. 2 — 19 August 2010
for its attributes. The bit assignments are:
for its attributes.
Table 654
Chapter 34: Appendix: Cortex-M3 user guide
for its attributes. The bit assignments are:
UM10360
© NXP B.V. 2010. All rights reserved.
Table
671.
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