LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 490
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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21.1 Basic configuration
21.2 Features
UM10360
User manual
The Timer 0, 1, 2, and 3 peripherals are configured using the following registers:
Remark: The four Timer/Counters are identical except for the peripheral base address. A
minimum of two Capture inputs and two Match outputs are pinned out for all four timers,
with a choice of multiple pins for each. Timer 2 brings out all four Match outputs.
1. Power: In the PCONP register
2. Peripheral clock: In the PCLKSEL0 register
3. Pins: Select timer pins through the PINSEL registers. Select the pin modes for the
4. Interrupts: See register T0/1/2/3MCR
5. DMA: Up to two match conditions can be used to generate timed DMA requests, see
•
•
•
•
•
UM10360
Chapter 21: LPC17xx Timer 0/1/2/3
Rev. 2 — 19 August 2010
Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled
(PCTIM2/3 = 0).
PCLKSEL1 register
port pins with timer functions through the PINMODE registers
match and capture events. Interrupts are enabled in the NVIC using the appropriate
Interrupt Set Enable register.
Table
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Counter or Timer operation
Up to two 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.
543.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
(Table
41), select PCLK_TIMER2/3.
(Table
46), set bits PCTIM0/1/2/3.
(Table
(Table
429) and T0/1/2/3CCR
40), select PCLK_TIMER0/1; in the
(Section
© NXP B.V. 2010. All rights reserved.
(Table
User manual
8.5).
430) for
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