LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 826

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
15.5
Chapter 16: LPC17xx CAN1/2
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.4
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.5.7
16.5.8
16.6
16.7
16.7.1
16.7.2
16.7.3
16.7.4
16.7.5
16.7.6
16.7.7
16.7.8
16.7.9
16.7.9.1
16.7.10
UM10360
User manual
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Basic configuration . . . . . . . . . . . . . . . . . . . . 343
CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 343
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 344
CAN controller architecture . . . . . . . . . . . . . 344
Memory map of the CAN block. . . . . . . . . . . 349
CAN controller registers . . . . . . . . . . . . . . . . 349
General CAN features . . . . . . . . . . . . . . . . . 343
CAN controller features . . . . . . . . . . . . . . . . 344
Acceptance filter features . . . . . . . . . . . . . . . 344
APB Interface Block (AIB) . . . . . . . . . . . . . . 345
Interface Management Logic (IML). . . . . . . . 345
Transmit Buffers (TXB) . . . . . . . . . . . . . . . . . 345
Receive Buffer (RXB) . . . . . . . . . . . . . . . . . 346
Error Management Logic (EML) . . . . . . . . . 347
Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . 347
Bit Stream Processor (BSP) . . . . . . . . . . . . . 347
CAN controller self-tests . . . . . . . . . . . . . . . . 347
Global self test . . . . . . . . . . . . . . . . . . . . . . . .348
Local self test . . . . . . . . . . . . . . . . . . . . . . . . .348
CAN Mode register (CAN1MOD - 0x4004 4000,
CAN2MOD - 0x4004 8000) . . . . . . . . . . . . . 351
CAN Command Register (CAN1CMR -
0x4004 x004, CAN2CMR - 0x4004 8004) . . 353
CAN Global Status Register (CAN1GSR -
0x4004 x008, CAN2GSR - 0x4004 8008) . . 354
RX error counter . . . . . . . . . . . . . . . . . . . . . . .356
TX error counter . . . . . . . . . . . . . . . . . . . . . . .356
CAN Interrupt and Capture Register (CAN1ICR -
0x4004 400C, CAN2ICR - 0x4004 800C). . . 357
CAN Interrupt Enable Register (CAN1IER -
0x4004 4010, CAN2IER - 0x4004 8010) . . . 360
CAN Bus Timing Register (CAN1BTR -
0x4004 4014, CAN2BTR - 0x4004 8014) . . . 361
Baud rate prescaler . . . . . . . . . . . . . . . . . . . .362
Synchronization jump width . . . . . . . . . . . . . .362
Time segment 1 and time segment 2 . . . . . . .362
CAN Error Warning Limit register (CAN1EWL -
0x4004 4018, CAN2EWL - 0x4004 8018) . . 362
CAN Status Register (CAN1SR - 0x4004 401C,
CAN2SR - 0x4004 801C) . . . . . . . . . . . . . . . 363
CAN Receive Frame Status register (CAN1RFS -
0x4004 4020, CAN2RFS - 0x4004 8020) . . . 365
ID index field . . . . . . . . . . . . . . . . . . . . . . . . . 365
CAN Receive Identifier register (CAN1RID -
0x4004 4024, CAN2RID - 0x4004 8024) . . . 365
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
16.7.11
16.7.12
16.7.13
16.7.14
16.7.15
16.7.16
16.7.17
16.7.18
16.8
16.8.1
16.8.2
16.8.3
16.8.4
16.9
16.9.1
16.9.2
16.9.3
16.10
16.11
16.11.1
16.11.2
16.11.3
16.11.4
16.12
16.13
16.14
16.14.1
CAN controller operation . . . . . . . . . . . . . . . 370
Centralized CAN registers . . . . . . . . . . . . . . 372
Global acceptance filter . . . . . . . . . . . . . . . . 373
Acceptance filter modes. . . . . . . . . . . . . . . . 373
Sections of the ID look-up table RAM . . . . . 374
ID look-up table RAM . . . . . . . . . . . . . . . . . . 375
Acceptance filter registers . . . . . . . . . . . . . . 377
CAN Receive Data register A (CAN1RDA -
0x4004 4028, CAN2RDA - 0x4004 8028) . . 366
CAN Receive Data register B (CAN1RDB -
0x4004 402C, CAN2RDB - 0x4004 802C). . 366
CAN Transmit Frame Information register
(CAN1TFI[1/2/3] - 0x4004 40[30/ 40/50],
CAN2TFI[1/2/3] - 0x4004 80[30/40/50]). . . . 367
Automatic transmit priority detection . . . . . . . 368
Tx DLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
CAN Transmit Identifier register (CAN1TID[1/2/3]
- 0x4004 40[34/44/54], CAN2TID[1/2/3] -
0x4004 80[34/44/54]) . . . . . . . . . . . . . . . . . . 368
CAN Transmit Data register A (CAN1TDA[1/2/3] -
0x4004 40[38/48/58], CAN2TDA[1/2/3] -
0x4004 80[38/48/58]) . . . . . . . . . . . . . . . . . . 369
CAN Transmit Data register B (CAN1TDB[1/2/3] -
0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] -
0x4004 80[3C/4C/5C]) . . . . . . . . . . . . . . . . . 369
CAN Sleep Clear register (CANSLEEPCLR -
0x400F C110) . . . . . . . . . . . . . . . . . . . . . . . 369
CAN Wake-up Flags register (CANWAKEFLAGS
- 0x400F C114) . . . . . . . . . . . . . . . . . . . . . . 370
Error handling . . . . . . . . . . . . . . . . . . . . . . . 370
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 371
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Transmit priority . . . . . . . . . . . . . . . . . . . . . . 371
Central Transmit Status Register (CANTxSR -
0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . 372
Central Receive Status Register (CANRxSR -
0x4004 0004) . . . . . . . . . . . . . . . . . . . . . . . . 372
Central Miscellaneous Status Register (CANMSR
- 0x4004 0008). . . . . . . . . . . . . . . . . . . . . . . 373
Acceptance filter Off mode. . . . . . . . . . . . . . 374
Acceptance filter Bypass mode . . . . . . . . . . 374
Acceptance filter Operating mode . . . . . . . . 374
FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . 374
Acceptance Filter Mode Register (AFMR -
0x4003 C000) . . . . . . . . . . . . . . . . . . . . . . . 377
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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