LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 786

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.5 Memory protection unit
This section describes the Memory protection unit (MPU).
The MPU divides the memory map into a number of regions, and defines the location,
size, access permissions, and memory attributes of each region. It supports:
The memory attributes affect the behavior of memory accesses to the region. The
Cortex-M3 MPU defines:
When memory regions overlap, a memory access is affected by the attributes of the
region with the highest number. For example, the attributes for region 7 take precedence
over the attributes of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The Cortex-M3 MPU memory map is unified. This means instruction accesses and data
accesses have same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor
generates a memory management fault. This causes a fault exception, and might cause
termination of the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based
on the process to be executed. Typically, an embedded OS uses the MPU for memory
protection.
Configuration of MPU regions is based on memory types, see
regions, types and
Table 679
cache behavior attributes that are not relevant to most microcontroller implementations.
See
Table 679. Memory attributes summary
Memory type
Strongly- ordered
Device
•
•
•
•
•
independent attribute settings for each region
overlapping regions
export of memory attributes to the system.
eight separate memory regions, 0-7
a background region.
Table 690
shows the possible MPU region attributes. These include Shareability and
for guidelines for programming such an implementation.
All information provided in this document is subject to legal disclaimers.
Shareability
-
Shared
attributes”.
Rev. 2 — 19 August 2010
Other attributes
-
-
Chapter 34: Appendix: Cortex-M3 user guide
Description
All accesses to Strongly-ordered
memory occur in program order. All
Strongly-ordered regions are
assumed to be shared.
Memory-mapped peripherals that
several processors share.
Section 34.3.2.1 “Memory
UM10360
© NXP B.V. 2010. All rights reserved.
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