LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 681

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.5.2.1 Syntax
34.2.5.2.2 Operation
34.2.5.2.3 Restrictions
34.2.5.2.4 Condition flags
34.2.5.2.5 Examples
34.2.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see
cond is an optional condition code, see
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations
on the values in Rn and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of
the corresponding bits in the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of
the corresponding bits in the value of Operand2.
Do not use SP and do not use PC.
If S is specified, these instructions:
•
•
•
AND: logical AND.
ORR: logical OR, or bit set.
EOR: logical Exclusive OR.
BIC: logical AND NOT, or bit clear.
ORN: logical OR NOT.
update the N and Z flags according to the result
can update the C flag during the calculation of Operand2, see
do not affect the V flag.
AND
ORREQ
ANDS
All information provided in this document is subject to legal disclaimers.
R9, R2, #0xFF00
R2, R0, R5
R9, R8, #0x19
Section 34.2.3.7 “Conditional
Rev. 2 — 19 August 2010
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.2.3.3
execution”.
for details of the options.
Section 34.2.3.3
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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