LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 338

IC ARM CORTEX MCU 512K 100-LQFP

LPC1767FBD100,551

Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr

Specifications of LPC1767FBD100,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4967
935289808551

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LPC1767FBD100,551
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NXP Semiconductors
Table 307: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description
Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description
UM10360
User manual
Bit
6:0
7
31:8
Bit
0
1
2
3
4
Symbol Description
-
TXEN
-
Symbol
NMMEN
RXDIS
AADEN
SEL
DCTRL
15.4.18 UART1 RS485 Control register (U1RS485CTRL - 0x4001 004C)
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as
soon as any preceding data has been sent. If this bit cleared to 0 while a character is being
sent, the transmission of that character is completed, but no further characters are sent until
this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the
THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects
that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software
handshaking, when it receives an XOFF character (DC3). Software can set this bit again
when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1)
character.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value Description
0
1
0
1
0
1
0
1
0
1
Although
control, it is strongly suggested to let UART1 hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
U1TER enables implementation of software and hardware flow control. When TXEn=1,
UART1 transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UART1 transmission will stop.
Table 307
The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.
address is detected when a received byte causes the UART to set the parity error
and generate an interrupt.
The receiver is enabled.
The receiver is disabled.
Auto Address Detect (AAD) is disabled.
Auto Address Detect (AAD) is enabled.
If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0
If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
Disable Auto Direction Control.
Enable Auto Direction Control.
RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an
Table 307
describes how to use TXEn bit in order to achieve software flow control.
All information provided in this document is subject to legal disclaimers.
describes how to use TxEn bit in order to achieve hardware flow
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
1
NA
Reset value
0
0
0
0
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