LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 432

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.6.2 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I
the data direction bit (R/W) should be 1 to indicate a read.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
Table
When the LPC17xx needs to acknowledge a received byte, the AA bit needs to be set
accordingly prior to clearing the SI bit and initiating the byte read. When the LPC17xx
needs to not acknowledge a received byte, the AA bit needs to be cleared prior to clearing
the SI bit and initiating the byte read.
Note that the last received byte is always followed by a "Not Acknowledge" from the
LPC17xx so that the master can signal the slave that the reading sequence is finished and
that it needs to issue a STOP or repeated START Command. Once the "Not Acknowledge
has been sent and the SI bit is set, the LPC17xx can send either a STOP (STO bit is set)
or a repeated START (STA bit is set). Then the SI bit is cleared to initiate the requested
operation.
Fig 85. Format in the Master Transmitter mode
Fig 86. Format of Master Receiver mode
S
from Master to Slave
from Slave to Master
S
from Master to Slave
from Slave to Master
399.
SLAVE ADDRESS
SLAVE ADDRESS
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
2
C Data register (I2DAT), and then clear the SI bit. In this case,
RW=1
RW=0
A
A
DATA
DATA
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
n bytes data received
n bytes data transmitted
A
A
Chapter 19: LPC17xx I2C0/1/2
DATA
DATA
UM10360
© NXP B.V. 2010. All rights reserved.
A/A
A
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P
P