LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 732

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Table 629.
Execution Program Status Register:
execution state bits for either the:
See the register summary in
Table 630.
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application
software are ignored. Fault handlers can examine EPSR value in the stacked PSR to
indicate the operation that is at fault. See
Bits
[31:9]
[8:0]
Bits
[31:27]
[26:25], [15:10]
[26:25], [15:10]
[24]
[23:16]
[9:0]
•
•
If-Then (IT) instruction
Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or
store multiple instruction.
Name
-
ISR_NUMBER
IPSR bit assignments
EPSR bit assignments
All information provided in this document is subject to legal disclaimers.
Name
-
ICI
IT
T
-
-
Rev. 2 — 19 August 2010
Function
Reserved
This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
17 = IRQ1, first device specific interrupt
.
.
255 = IRQ243 (last implemented interrupt depends on device)
see
Function
Section 34.2.9.3
Reserved.
Reserved.
Interruptible-continuable instruction bits, see
Indicates the execution state bits of the IT instruction, see
Always set to 1.
Reserved.
Table 626
Section 34.3.3.2
The EPSR contains the Thumb state bit, and the
for the EPSR attributes. The bit assignments are:
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.3.3.7
“IT”.
for more information.
Section
UM10360
© NXP B.V. 2010. All rights reserved.
.
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