LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 816

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Fig 88. Format of Slave Receiver mode . . . . . . . . . . . .434
Fig 89. Format of Slave Transmitter mode . . . . . . . . . .434
Fig 90. I
Fig 91. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .437
Fig 92. Serial clock synchronization. . . . . . . . . . . . . . . .437
Fig 93. Format and states in the Master Transmitter
Fig 94. Format and states in the Master Receiver
Fig 95. Format and states in the Slave Receiver mode .455
Fig 96. Format and states in the Slave Transmitter
Fig 97. Simultaneous repeated START conditions from two
Fig 98. Forced access to a busy I
Fig 99. Recovering from a bus obstruction caused by a
Fig 100. Simple I2S configurations and bus timing . . . . .475
Fig 101. Typical transmitter master mode, with or without
Fig 102. Transmitter master mode sharing the receiver
Fig 103. 4-wire transmitter master mode sharing the receiver
Fig 104. Typical transmitter slave mode . . . . . . . . . . . . .485
Fig 105. Transmitter slave mode sharing the receiver
Fig 106. 4-wire transmitter slave mode sharing the receiver
Fig 107. Typical receiver master mode, with or without MCLK
Fig 108. Receiver master mode sharing the transmitter
Fig 109. 4-wire receiver master mode sharing the transmitter
Fig 110. Typical receiver slave mode . . . . . . . . . . . . . . .487
Fig 111. Receiver slave mode sharing the transmitter
Fig 112. 4-wire receiver slave mode sharing the transmitter
Fig 113. FIFO contents for various I
Fig 114. A timer cycle in which PR=2, MRx=6, and both
Fig 115. A timer Cycle in Which PR=2, MRx=6, and both
Fig 116. Timer block diagram . . . . . . . . . . . . . . . . . . . . .500
Fig 117. RI timer block diagram. . . . . . . . . . . . . . . . . . . .503
Fig 118. System Tick Timer block diagram . . . . . . . . . . .505
Fig 119. PWM block diagram. . . . . . . . . . . . . . . . . . . . . . 511
Fig 120. Sample PWM waveforms . . . . . . . . . . . . . . . . .512
Fig 121. MCPWM Block Diagram . . . . . . . . . . . . . . . . . .523
Fig 122. Edge-aligned PWM waveform without dead time,
Fig 123. Center-aligned PWM waveform without dead time,
Fig 124. Edge-aligned PWM waveform with dead time,
Fig 125. Center-aligned waveform with dead time,
UM10360
User manual
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .456
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464
LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . .464
MCLK output . . . . . . . . . . . . . . . . . . . . . . . . . . .485
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .485
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .485
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .485
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .486
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .487
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .487
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .487
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .488
interrupt and reset on match are enabled. . . . . .499
interrupt and stop on match are enabled . . . . . .499
POLA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537
POLA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
POLA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
2
C serial interface block diagram . . . . . . . . . . .435
2
C-bus. . . . . . . . . . . .464
2
S modes. . . . . . . . .489
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Fig 126. Three-phase DC mode sample waveforms . . . 541
Fig 127. Three-phase AC mode sample waveforms, edge
Fig 128. Encoder interface block diagram . . . . . . . . . . . 544
Fig 129. Quadrature Encoder Basic Operation. . . . . . . . 546
Fig 130. RTC domain conceptual diagram . . . . . . . . . . . 559
Fig 131. RTC functional block diagram. . . . . . . . . . . . . . 559
Fig 132. Watchdog block diagram . . . . . . . . . . . . . . . . . 573
Fig 133. DAC control with DMA interrupt and timer . . . . 585
Fig 134. DMA controller block diagram. . . . . . . . . . . . . . 587
Fig 135. LLI example . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Fig 136. Map of lower memory . . . . . . . . . . . . . . . . . . . . 616
Fig 137. Boot process flowchart . . . . . . . . . . . . . . . . . . . 619
Fig 138. IAP parameter passing . . . . . . . . . . . . . . . . . . . 632
Fig 139. Algorithm for generating a 128 bit signature. . . 640
Fig 140. Typical Cortex-M3 implementation . . . . . . . . . . 644
Fig 141. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Fig 142. LSR#3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Fig 143. LSL#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Fig 144. ROR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Fig 145. RRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Fig 146. Bit-band mapping . . . . . . . . . . . . . . . . . . . . . . . 742
Fig 147. Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
aligned PWM mode. . . . . . . . . . . . . . . . . . . . . . 542
Chapter 35: Supplementary information
UM10360
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