LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 530

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 466. MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068) bit description
UM10360
User manual
Bit
31:0
Value Description
1
0
25.7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054)
25.7.3.3 MCPWM Interrupt Enable clear address (MCINTEN_CLR - 0x400B 8058)
25.7.3.4 MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068)
25.7.3.5 MCPWM Interrupt Flags set address (MCINTF_SET - 0x400B 806C)
25.7.3.6 MCPWM Interrupt Flags clear address (MCINTF_CLR - 0x400B 8070)
See
If the corresponding bit in MCINTEN is 1, the MCPWM module is asserting its interrupt request to
the Interrupt Controller.
This interrupt source is not contributing to the MCPWM interrupt request.
Table 462
Writing ones to this write-only address sets the corresponding bits in MCINTEN, thus
enabling interrupts.
Table 464. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit
Writing ones to this write-only address clears the corresponding bits in MCINTEN, thus
disabling interrupts.
Table 465. PWM interrupt enable clear register (MCINTEN_CLR - address 0x400B 8058) bit
The MCINTF register includes all MCPWM interrupt flags, which are set when the
corresponding hardware event occurs, or when ones are written to the MCINTF_SET
address. When corresponding bits in this register and MCINTEN are both 1, the MCPWM
asserts its interrupt request to the Interrupt Controller module. This address is read-only,
but the bits in the underlying register can be modified by writing ones to addresses
MCINTF_SET and MCINTF_CLR.
Writing one(s) to this write-only address sets the corresponding bit(s) in MCINTF, thus
possibly simulating hardware interrupt(s).
Table 467. MCPWM Interrupt Flags set address (PWMINTF_SET - 0x400B 806C) bit
Writing one(s) to this write-only address sets the corresponding bit(s) in MCINTF, thus
clearing the corresponding interrupt request(s). This is typically done in interrupt service
routines.
Bit
31:0
Bit
31:0
Bit
31:0
Description
register, thus possibly simulating hardware interrupt(s). See
Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF
for the bit allocation.
Description
Writing ones to this address sets the corresponding bits in MCINTEN, thus enabling
interrupts. See
Description
Writing ones to this address clears the corresponding bits in MCINTEN, thus disabling
interrupts. See
description
description
description
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Table
Table
Rev. 2 — 19 August 2010
462.
462.
Chapter 25: LPC17xx Motor control PWM
Table
462.
UM10360
© NXP B.V. 2010. All rights reserved.
530 of 840
Reset
value
0