LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 482

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 417: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description
Table 418: Receive Mode Control register (I2SRXMODE - 0x400A 8034) bit description
UM10360
User manual
Bit
1:0
2
3
31:4
Bit
1:0
2
3
31:4
Symbol
TXCLKSEL
TX4PIN
TXMCENA
-
Symbol
RXCLKSEL
RX4PIN
RXMCENA
-
20.5.14 Receive Mode Control register (I2SRXMODE - 0x400A 8034)
Value Description
00
01
10
11
Value Description
00
01
10
11
The Receive Mode Control register contains additional controls for receive clock source,
enabling the 4-pin mode, and how MCLK is used. See
useful mode combinations.
Clock source selection for the transmit bit clock divider.
Select the TX fractional rate divider clock output as the source
Reserved
Select the RX_MCLK signal as the TX_MCLK clock source
Reserved
Transmit 4-pin mode selection. When 1, enables 4-pin mode.
Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1,
output of TX_MCLK is enabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Clock source selection for the receive bit clock divider.
Select the RX fractional rate divider clock output as the source
Reserved
Select the TX_MCLK signal as the RX_MCLK clock source
Reserved
Receive 4-pin mode selection. When 1, enables 4-pin mode.
Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1,
output of RX_MCLK is enabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 20.7
Chapter 20: LPC17xx I2S
for a summary of
UM10360
© NXP B.V. 2010. All rights reserved.
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0
0
Reset
Value
0
0
NA
Reset
Value
0
0
NA