LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 41

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Table 25.
The PLL0 output frequency (when PLL0 is both active and connected) is given by:
F
PLL inputs and settings must meet the following:
The equation can be solved for other PLL parameters:
M = (F
N = (2 × M × F
F
Allowed values for M:
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are
allowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65
additional M values have been selected for supporting baud rate generation, CAN
operation, and obtaining integer MHz frequencies. These values are shown in
Parameter
F
F
N
M
F
CCO
IN
•
•
IN
CCO
REF
= (F
F
F
IN
CCO
= (2 × M × F
CCO
is in the range of 32 kHz to 50 MHz.
CCO
is in the range of 275 MHz to 550 MHz.
PLL frequency parameter
× N) / (2 × F
× N) / (2 × M)
Description
the frequency of PLLCLKIN from the Clock Source Selection Multiplexer.
the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator)
PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG
NSEL0 field + 1). N is an integer from 1 through 32.
PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG
MSEL0 field + 1). Not all potential values are supported. See below.
PLL internal reference frequency, F
IN
All information provided in this document is subject to legal disclaimers.
) / F
IN
) / N
CCO
Rev. 2 — 19 August 2010
IN
)
Chapter 4: LPC17xx Clocking and power control
IN
divided by N.
UM10360
© NXP B.V. 2010. All rights reserved.
Table
41 of 840
26.