LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 47
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
4.6 PLL1 (Phase Locked Loop 1)
UM10360
User manual
4.6.1 PLL1 register description
PLL1 receives its clock input from the main oscillator only and can be used to provide a
fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the
possibility of generating the USB clock from PLL0.
PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be
supplied by PLL0 if everything is set up to provide 48 MHz through that route. If PLL1 is
enabled and connected via the PLL1CON register (see
selected to drive the USB subsystem (see
PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values
are controlled by the PLL1CFG register. These two registers are protected in order to
prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection
is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL1FEED register.
PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input
frequency is multiplied up to the range of 48 MHz for the USB clock using a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB,
the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz
to 320 MHz, so there is an additional divider in the loop to keep the CCO within its
frequency range while PLL1 is providing the desired output frequency. The output divider
may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum
output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A
block diagram of PLL1 is shown in
PLL1 is controlled by the registers shown in
Writes to any unused bits are ignored. A read of any unused bits will return a logic zero.
Warning: Improper setting of PLL1 values may result in incorrect operation of the
USB subsystem!
Table 29.
Name
PLL1CON
PLL1 registers
Description
PLL1 Control Register. Holding register for
updating PLL1 control bits. Values written to this
register do not take effect until a valid PLL1 feed
sequence has taken place.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Figure
Chapter 4: LPC17xx Clocking and power control
10.
Figure
Table
7).
29. More detailed descriptions follow.
Section
Access Reset
R/W
4.6.2), it is automatically
value
0
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
Address
0x400F C0A0
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