LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 771

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.3.6 Application Interrupt and Reset Control Register
Table 658. VTOR bit assignments
When setting TBLOFF, you must align the offset to the number of exception entries in the
vector table. The recommended alignment is 256 words, allowing for 128 interrupts.
Remark: Table alignment requirements mean that bits[7:0] of the table offset are always
zero.
The AIRCR provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. See the register summary in
and
To write to this register, you must write 0x5VA to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are shown in
Table 659. AIRCR bit assignments
Bits
[31:30]
[29:8]
[7:0]
Bits
[31:16]
[15]
[14:11]
[10:8]
[7:3]
Table 659
Name
Write:
VECTKEYSTAT
Read: VECTKEY
ENDIANESS
-
PRIGROUP
-
Name
-
TBLOFF
-
for its attributes.
All information provided in this document is subject to legal disclaimers.
Function
Reserved.
Vector table base offset field. It contains bits[29:8] of the offset of the table
base from the bottom of the memory map.
Remark: Bit[29] determines whether the vector table is in the code or
SRAM memory region:
Bit[29] is sometimes called the TBLBASE bit.
Reserved.
Rev. 2 — 19 August 2010
•
•
0 = code
1 = SRAM.
Type
RW
RO
-
R/W
-
Table
Function
Register key:
Reads as 0x05FA
On writes, write 0x5FA to VECTKEY, otherwise the write is
ignored.
Data endianness bit:
0 = Little-endian.
Reserved
Interrupt priority grouping field. This field determines the
split of group priority from subpriority, see
Section
Reserved.
659.
Chapter 34: Appendix: Cortex-M3 user guide
34.4.3.6.1.
UM10360
© NXP B.V. 2010. All rights reserved.
Table 654
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