LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 671
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.4.6.1 Syntax
34.2.4.6.2 Operation
34.2.4.6 LDM and STM
Load and Store Multiple registers.
op{addr_mode}{cond} Rn{!}, reglist
where:
op is one of:
addr_mode is any one of the following:
cond is an optional condition code, see
Rn is the register on which the memory addresses are based.
! is an optional writeback suffix. If ! is present the final address, that is loaded from or
stored to, is written back into Rn.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can
contain register ranges. It must be comma separated if it contains more than one register
or register range, see
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full
Descending stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending
stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty
Ascending stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending
stacks
LDM instructions load the registers in reglist with word values from memory addresses
based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses
based on Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses
are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of
registers in reglist. The accesses happens in order of increasing register numbers, with
the lowest numbered register using the lowest memory address and the highest number
register using the highest memory address. If the writeback suffix is specified, the value of
Rn + 4 * (n-1) is written back to Rn.
LDM: Load Multiple registers.
STM: Store Multiple registers.
IA: Increment address After each access. This is the default.
DB: Decrement address Before each access.
All information provided in this document is subject to legal disclaimers.
Section
Rev. 2 — 19 August 2010
34.2.4.6.5.
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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