LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 401

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

17.1 Basic configuration
17.2 Features
17.3 SPI overview
UM10360
User manual
The SPI is configured using the following registers:
Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is
included as a legacy peripheral. Only one of these peripherals can be used at the any one
time.
SPI is a full duplex serial interface. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.
1. Power: In the PCONP register
2. Clock: In the PCLKSEL0 register
3. Pins: The SPI pins are configured using both PINSEL0
4. Interrupts: The SPI interrupt flag is enabled using the S0SPINT[0] bit
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UM10360
Chapter 17: LPC17xx SPI
Rev. 2 — 19 August 2010
Remark: On reset, the SPI is enabled (PCSPI = 1).
clock must be an even number greater than or equal to 8 (see
(Table
configure the SPI CLK pin. PINSEL1[1:0], PINSEL1[3:2] and PINSEL1[5:4] are used
to configure the pins SSEL, MISO and MOSI, respectively.
The SPI interrupt flag must be enabled in the NVIC, see
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex Communication.
SPI master or slave.
Maximum data bit rate of one eighth of the peripheral clock rate.
8 to 16 bits per transfer.
80), as well as the PINMODE
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
(Table
(Table
(Section
46), set bit PCSPI.
40), set bit PCLK_SPI. In master mode, the
8.4) register. PINSEL0[31:30] is used to
(Table
Table
79) and PINSEL1
Section
50.
© NXP B.V. 2010. All rights reserved.
(Section
User manual
17.7.4).
401 of 840
17.7.7).