LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 577

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 531: A/D Control Register (AD0CR - address 0x4003 4000) bit description
UM10360
User manual
Bit
7:0
15:8
16
20:17 -
21
23:22 -
26:24 START
27
31:28 -
Symbol Value Description
SEL
CLKDIV
BURST
PDN
EDGE
29.5.1 A/D Control Register (AD0CR - 0x4003 4000)
1
0
1
0
000
001
010
011
100
101
110
111
1
0
Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0
selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of
these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is
allowed. All zeroes is equivalent to 0x01.
The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for
the A/D converter, which should be less than or equal to 13 MHz. Typically, software
should program the smallest value in this field that yields a clock of 13 MHz or slightly
less, but in certain cases (such as a high-impedance analog source) a slower clock may
be desirable.
The AD converter does repeated conversions at up to 200 kHz, scanning (if necessary)
through the pins selected by bits set to ones in the SEL field. The first conversion after the
start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits
(pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the
conversion that’s in progress when this bit is cleared will be completed.
Remark: START bits must be 000 when BURST = 1 or conversions will not start.
Conversions are software controlled and require 65 clocks.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The A/D converter is operational.
The A/D converter is in power-down mode.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
No start (this value should be used when clearing PDN to 0).
Start conversion now.
Start conversion when the edge selected by bit 27 occurs on the P2.10 / EINT0 / NMI pin.
Start conversion when the edge selected by bit 27 occurs on the P1.27 / CLKOUT /
USB_OVRCRn / CAP0.1 pin.
Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does
not require that the MAT0.1 function appear on a device pin.
Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not
possible to cause the MAT0.3 function to appear on a device pin.
Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does
not require that the MAT1.0 function appear on a device pin.
Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does
not require that the MAT1.1 function appear on a device pin.
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a falling edge on the selected CAP/MAT signal.
Start conversion on a rising edge on the selected CAP/MAT signal.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
0x01
0
0
NA
0
NA
0
0
NA