LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 827

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
16.14.2
16.14.3
16.14.4
16.14.5
16.14.6
16.14.7
16.14.8
16.14.9
16.14.10 LUT Error register (LUTerr - 0x4003 C01C) . 380
16.14.11 Global FullCANInterrupt Enable register (FCANIE
16.14.12 FullCAN Interrupt and Capture registers
16.15
16.15.1
16.16
16.16.1
16.16.2
16.16.2.1 FullCAN message interrupt enable bit . . . . . 386
16.16.2.2 Message lost bit and CAN channel number . 387
16.16.2.3 Setting the interrupt pending bits (IntPnd 63 to
16.16.2.4 Clearing the interrupt pending bits (IntPnd 63 to
16.16.2.5 Setting the message lost bit of a FullCAN
16.16.2.6 Clearing the message lost bit of a FullCAN
Chapter 17: LPC17xx SPI
17.1
17.2
17.3
17.4
17.5
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.7
UM10360
User manual
Configuration and search algorithm . . . . . . 381
FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . . 382
Basic configuration . . . . . . . . . . . . . . . . . . . . 401
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
SPI overview. . . . . . . . . . . . . . . . . . . . . . . . . . 401
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 402
SPI data transfers . . . . . . . . . . . . . . . . . . . . . 402
SPI peripheral details . . . . . . . . . . . . . . . . . . 404
Register description . . . . . . . . . . . . . . . . . . . 406
Section configuration registers . . . . . . . . . . . 377
Standard Frame Individual Start Address register
(SFF_sa - 0x4003 C004) . . . . . . . . . . . . . . . 378
Standard Frame Group Start Address register
(SFF_GRP_sa - 0x4003 C008) . . . . . . . . . . 378
Extended Frame Start Address register (EFF_sa -
0x4003 C00C) . . . . . . . . . . . . . . . . . . . . . . . 378
Extended Frame Group Start Address register
(EFF_GRP_sa - 0x4003 C010) . . . . . . . . . . 379
End of AF Tables register (ENDofTable -
0x4003 C014) . . . . . . . . . . . . . . . . . . . . . . . . 379
Status registers . . . . . . . . . . . . . . . . . . . . . . . 379
LUT Error Address register (LUTerrAd -
0x4003 C018) . . . . . . . . . . . . . . . . . . . . . . . . 380
- 0x4003 C020). . . . . . . . . . . . . . . . . . . . . . . 380
(FCANIC0 - 0x4003 C024 and FCANIC1 -
0x4003 C028) . . . . . . . . . . . . . . . . . . . . . . . . 380
Acceptance filter search algorithm . . . . . . . . 381
FullCAN message layout . . . . . . . . . . . . . . . 384
FullCAN interrupts . . . . . . . . . . . . . . . . . . . . 386
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
message object (MsgLost 63 to 0) . . . . . . . . 388
message object (MsgLost 63 to 0) . . . . . . . . 388
General information . . . . . . . . . . . . . . . . . . . 404
Master operation. . . . . . . . . . . . . . . . . . . . . . 404
Slave operation. . . . . . . . . . . . . . . . . . . . . . . 405
Exception conditions. . . . . . . . . . . . . . . . . . . 405
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
16.16.3
16.16.3.1 Scenario 1: Normal case, no message lost . 388
16.16.3.2 Scenario 2: Message lost. . . . . . . . . . . . . . . 389
16.16.3.3 Scenario 3: Message gets overwritten indicated
16.16.3.4 Scenario 3.1: Message gets overwritten indicated
16.16.3.5 Scenario 3.2: Message gets overwritten indicated
16.16.3.6 Scenario 4: Clearing Message Lost bit . . . . 392
16.17
16.17.1
16.17.2
16.17.3
16.17.4
16.17.5
16.17.6
16.17.7
16.17.8
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Examples of acceptance filter tables and ID
index values. . . . . . . . . . . . . . . . . . . . . . . . . . 393
Set and clear mechanism of the FullCAN
interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
by Semaphore bits . . . . . . . . . . . . . . . . . . . . 390
by Semaphore bits and Message Lost. . . . . 390
by Message Lost . . . . . . . . . . . . . . . . . . . . . 391
Example 1: only one section is used . . . . . . 393
Example 2: all sections are used . . . . . . . . . 393
Example 3: more than one but not all sections are
used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Configuration example 4 . . . . . . . . . . . . . . . 394
Configuration example 5 . . . . . . . . . . . . . . . 394
Configuration example 6 . . . . . . . . . . . . . . . 395
Explicit standard frame format identifier section
(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 396
Group of standard frame format identifier section
(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 396
Explicit extended frame format identifier section
(29-bit CAN ID,
Group of extended frame format identifier section
(29-bit CAN ID,
Configuration example 7 . . . . . . . . . . . . . . . 397
FullCAN explicit standard frame format identifier
section (11-bit CAN ID) . . . . . . . . . . . . . . . . . 398
Explicit standard frame format identifier section
(11-bit CAN ID) . . . . . . . . . . . . . . . . . . . . . . . 398
FullCAN message object data section . . . . . . 398
Look-up table programming guidelines . . . . 399
SPI Control Register (S0SPCR - 0x4002
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
SPI Status Register (S0SPSR - 0x4002
0004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
SPI Data Register (S0SPDR - 0x4002 0008) 408
SPI Clock Counter Register (S0SPCCR -
0x4002 000C) . . . . . . . . . . . . . . . . . . . . . . . 408
SPI Test Control Register (SPTCR - 0x4002
0010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
SPI Test Status Register (SPTSR - 0x4002
0014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Chapter 35: Supplementary information
Figure
Figure
72) . . . . . . . . . . . . . . . 396
72) . . . . . . . . . . . . . . . 396
UM10360
© NXP B.V. 2010. All rights reserved.
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