LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 563

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description
Table 510. Counter Increment Interrupt Register (CIIR - address 0x4002 400C) bit description
UM10360
User manual
Bit
1
3:2
4
31:5
Bit
0
1
2
3
4
5
6
7
31:8
Symbol
CTCRST
-
CCALEN
-
Symbol
IMSEC
IMMIN
IMHOUR
IMDOM
IMDOW
IMDOY
IMMON
IMYEAR
-
27.6.2.3 Counter Increment Interrupt Register (CIIR - 0x4002 400C)
27.6.2.4 Alarm Mask Register (AMR - 0x4002 4010)
Value Description
1
0
1
0
Description
When 1, an increment of the Second value generates an interrupt.
When 1, an increment of the Minute value generates an interrupt.
When 1, an increment of the Hour value generates an interrupt.
When 1, an increment of the Day of Month value generates an interrupt.
When 1, an increment of the Day of Week value generates an interrupt.
When 1, an increment of the Day of Year value generates an interrupt.
When 1, an increment of the Month value generates an interrupt.
When 1, an increment of the Year value generates an interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
1 to bit 0 of the Interrupt Location Register (ILR[0]).
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table 511
alarm function, every non-masked alarm register must match the corresponding time
counter for an interrupt to be generated. The interrupt is generated only when the counter
comparison first changes from no match to match. The interrupt is removed when a one is
written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are
set, then the alarm is disabled.
CTC Reset.
When one, the elements in the internal oscillator divider are reset, and remain reset until
CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the
32.768 kHz crystal. The state of the divider is not visible to software.
No effect.
Internal test mode controls. These bits must be 0 for normal RTC operation.
Calibration counter enable.
The calibration counter is disabled and reset to zero.
The calibration counter is enabled and counting, using the 1 Hz clock. When the
calibration counter is equal to the value of the CALIBRATION register, the counter resets
and repeats counting up to the value of the CALIBRATION register. See
and
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Section
shows the relationship between the bits in the AMR and the alarms. For the
27.6.5.
All information provided in this document is subject to legal disclaimers.
Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers
Rev. 2 — 19 August 2010
Section 27.6.4.2
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
0
NC
NC
NA
0
0
0
0
0
0
0
0
Reset
value
NA