LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 642

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
33.5 Debug Notes
UM10360
User manual
Table 608. JTAG pin description
Table 609. Serial Wire Debug pin description
Table 610. Parallel Trace pin description
Important: The user should be aware of certain limitations during debugging. The most
important is that, due to limitations of the Cortex-M3 integration, the LPC17xx cannot
wake up in the usual manner from Deep Sleep and Power-down modes. It is
recommended not to use these modes during debug.
Pin Name
TCK
TMS
TDI
TDO
TRST
RTCK
Pin Name
SWDCLK
SWDIO
SWO
Pin Name
TRACECLK
TRACEDATA[3:0] Output
All information provided in this document is subject to legal disclaimers.
Type
Input
Input
Input
Output
Input
Output
Type
Input
Input /
Output
Output
Type
Input
Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace
Rev. 2 — 19 August 2010
Description
JTAG Test Clock. This pin is the clock for debug logic when in the
JTAG debug mode.
JTAG Test Mode Select. The TMS pin selects the next state in the
TAP state machine.
JTAG Test Data In. This is the serial data input for the shift register.
JTAG Test Data Output. This is the serial data output from the shift
register. Data is shifted out of the device on the negative edge of the
TCK signal.
JTAG Test Reset. The TRST pin can be used to reset the test logic
within the debug logic.
JTAG Returned Test Clock. This is an extra signal added to the
JTAG port, and is included for backward pin compatibility with
LPC23xx series devices that share the same pinout as this device.
RTCK is not normally used with the Cortex-M3.
For designs based on ARM7TDMI-S processor core, this signal
could be used by external JTAG host interface logic to maintain
synchronization with targets having a slow or varying clock
frequency. For details refer to "Multi-ICE System Design
considerations Application Note 72 (ARM DAI 0072A)".
Description
Serial Wire Clock. This pin is the clock for debug logic when in the
Serial Wire Debug mode.
Serial wire debug data input/output. The SWDIO pin is used by an
external debug tool to communicate with and control the Cortex-M3
CPU.
Serial Wire Output. The SWO pin optionally provides data from the
ITM and/or the ETM for an external debug tool to evaluate.
Description
Trace Clock. This pin provides the sample clock for trace data on
the TRACEDATA pins when tracing is enabled by an external debug
tool.
Trace Data bits 3 to 0. These pins provide ETM trace data when
tracing is enabled by an external debug tool. The debug tool can
then interpret the compressed information and make it available to
the user.
UM10360
© NXP B.V. 2010. All rights reserved.
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