LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 710
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.9.3.4 Condition flags
34.2.9.3.5 Example
Other restrictions when using an IT block are:
Remark: Your assembler might place extra restrictions on the use of IT blocks, such as
prohibiting the use of assembler directives within them.
This instruction does not change the flags.
•
•
•
•
•
CPSID and CPSIE.
a branch or any instruction that modifies the PC must either be outside an IT block or
must be the last instruction inside the IT block. These are:
– ADD PC, PC, Rm
– MOV PC, Rm
– B, BL, BX, BLX
– any LDM, LDR, or POP instruction that writes to the PC
– TBB and TBH
do not branch to any instruction inside an IT block, except when returning from an
exception handler
all conditional instructions except Bcond must be inside an IT block. Bcond can be
either outside or inside an IT block but has a larger branch range if it is inside one
each instruction inside the IT block must specify a condition code suffix that is either
the same or logical inverse as for the other instructions in the block.
ITTE
ANDNE R0, R0, R1
ADDSNE R2, R2, #1
MOVEQ R2, R3
CMP
ITE
ADDGT R1, R0, #55 ; Convert 0xA -> 'A'
ADDLE R1, R0, #48 ; Convert 0x0 -> '0'
IT
ADDGT R1, R1, #1
ITTEE EQ
MOVEQ R0, R1
ADDEQ R2, R2, #10 ; Conditional add
ANDNE R3, R3, #1
BNE.W dloop
All information provided in this document is subject to legal disclaimers.
NE
R0, #9
GT
GT
Rev. 2 — 19 August 2010
; Next 3 instructions are conditional
; ANDNE does not update condition flags
; ADDSNE updates condition flags
; Conditional move
; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
; Next 2 instructions are conditional
; IT block with only one conditional instruction
; Increment R1 conditionally
; Next 4 instructions are conditional
; Conditional move
; Conditional AND
; Branch instruction can only be used in the last
; instruction of an IT block
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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