LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 528

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 457. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description
Table 458. MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description
UM10360
User manual
Bit
31:0
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
31:24 -
Symbol
CAP0MCI0_RE
CAP0MCI0_FE
CAP0MCI1_RE
CAP0MCI1_FE
CAP0MCI2_RE
CAP0MCI2_FE
CAP1MCI0_RE
CAP1MCI0_FE
CAP1MCI1_RE
CAP1MCI1_FE
CAP1MCI2_RE
CAP1MCI2_FE
CAP2MCI0_RE
CAP2MCI0_FE
CAP2MCI1_RE
CAP2MCI1_FE
CAP2MCI2_RE
CAP2MCI2_FE
RT0
RT1
RT2
HNFCAP0
HNFCAP1
HNFCAP2
Description
Writing ones to this address clears the corresponding bits in the MCCON register. See
25.7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008)
25.7.2.1 MCPWM Capture Control read address (MCCAPCON - 0x400B 800C)
25.7.2 MCPWM Capture Control register
Writing ones to this write-only address clears the corresponding bits in MCCON.
The MCCAPCON register controls detection of events on the MCI0-2 inputs for all
MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on
any or all of the three channels. This address is read-only, but the underlying register can
be modified by writing to addresses MCCAPCON_SET and MCCAPCON_CLR.
Description
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.
A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.
A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.
A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.
A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.
A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.
If this bit is 1, TC0 is reset by a channel 0 capture event.
If this bit is 1, TC1 is reset by a channel 1 capture event.
If this bit is 1, TC2 is reset by a channel 2 capture event.
Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in
Section
Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in
Section
Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in
Section
Reserved.
25.8.4.
25.8.4.
25.8.4.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 25: LPC17xx Motor control PWM
Table
455.
UM10360
© NXP B.V. 2010. All rights reserved.
528 of 840
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-