LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 765

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.2.10 NVIC design hints and tips
34.4.2.9.1 Hardware and software control of interrupts
When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see
deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of
the following reasons:
A pending interrupt remains pending until one of the following:
Ensure software uses correctly aligned register accesses. The processor does not
support unaligned accesses to NVIC registers. See the individual register descriptions for
the supported access sizes.
A interrupt can enter pending state even it is disabled.
Before programming VTOR to relocate the vector table, ensure the vector table entries of
the new vector table are setup for fault handlers, NMI and all enabled exception like
interrupts. For more information see
•
•
•
•
•
the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
the NVIC detects a rising edge on the interrupt signal
software writes to the corresponding interrupt set-pending register bit, see
or to the STIR to make an SGI pending, see
The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the
interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, state of the interrupt changes to:
– inactive, if the state was pending
– active, if the state was active and pending.
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
is pulsed the state of the interrupt changes to pending and active. In this case,
when the processor returns from the ISR the state of the interrupt changes to
pending, which might cause the processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the
processor returns from the ISR the state of the interrupt changes to inactive.
Section
All information provided in this document is subject to legal disclaimers.
34.4.2.9.1. For a level-sensitive interrupt, if the signal is not
Rev. 2 — 19 August 2010
Table
Chapter 34: Appendix: Cortex-M3 user guide
658.
Table
652.
UM10360
© NXP B.V. 2010. All rights reserved.
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