LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 798

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Condition field — A four-bit field in an instruction that specifies a condition under which
the instruction can execute.
Context — The environment that each process operates in for a multitasking operating
system. In ARM processors, this is limited to mean the physical address range that it can
access in memory and the associated memory access permissions.
Coprocessor — A processor that supplements the main processor. Cortex-M3 does not
support any coprocessors.
Debugger — A debugging system that includes a program, used to detect, locate, and
correct software faults, together with custom hardware that supports software debugging.
Direct Memory Access (DMA) — An operation that accesses main memory directly,
without the processor performing any accesses to the data concerned.
Doubleword — A 64-bit data item. The contents are taken as being an unsigned integer
unless otherwise stated.
Doubleword-aligned — A data item having a memory address that is divisible by eight.
Endianness — Byte ordering. The scheme that determines the order that successive
bytes of a data word are stored in memory. An aspect of the system’s memory mapping.
See also Little-endian and Big-endian.
Exception — An event that interrupts program execution. When an exception occurs, the
processor suspends the normal program flow and starts execution at the address
indicated by the corresponding exception vector. The indicated address contains the first
instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated system
exception. Faults include attempting an invalid memory access, attempting to execute an
instruction in an invalid processor state, and attempting to execute an undefined
instruction.
Exception service routine — See also Interrupt handler.
Exception vector — See also Interrupt vector.
Flat address mapping — A system of organizing memory in which each physical
address in the memory space is the same as the corresponding virtual address.
Halfword — A 16-bit data item.
Illegal instruction — An instruction that is architecturally Undefined.
Implementation-defined — The behavior is not architecturally defined, but is defined and
documented by individual implementations.
Implementation-specific — The behavior is not architecturally defined, and does not
have to be documented by individual implementations. Used when there are a number of
implementation options available and the option chosen does not affect software
compatibility.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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