LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 578

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 532: A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description
Table 533: A/D Status register (AD0INTEN - address 0x4003 400C) bit description
UM10360
User manual
Bit
3:0
15:4
23:16
26:24
29:27
30
31
Bit
0
1
2
Symbol
ADINTEN0
ADINTEN1
ADINTEN2
Symbol
-
RESULT
-
CHN
-
OVERRUN
DONE
29.5.2 A/D Global Data Register (AD0GDR - 0x4003 4004)
29.5.3 A/D Interrupt Enable register (AD0INTEN - 0x4003 400C)
The A/D Global Data Register holds the result of the most recent A/D conversion that has
completed, and also includes copies of the status flags that go with that conversion.
Results of ADC conversion can be read in one of two ways. One is to use the A/D Global
Data Register to read all data from the ADC. Another is to use the
Registers
OVERRUN flags can otherwise get out of synch between the AD0GDR and the
Channel Data Register
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Value
0
1
0
1
0
1
Description
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
When DONE is 1, this field contains a binary fraction representing the voltage on
the AD0[n] pin selected by the SEL field, as it falls within the range of V
V
equal to, or close to that on V
input was close to, equal to, or greater than that on V
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
These bits contain the channel from which the RESULT bits were converted (e.g.
000 identifies channel 0, 001 channel 1...).
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
This bit is 1 in burst mode if the results of one or more conversions was (were) lost
and overwritten before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared when this
register is read and when the ADCR is written. If the ADCR is written while a
conversion is still in progress, this bit is set and a new conversion is started.
REFN
Description
Completion of a conversion on ADC channel 0 will not generate an interrupt.
Completion of a conversion on ADC channel 0 will generate an interrupt.
Completion of a conversion on ADC channel 1 will not generate an interrupt.
Completion of a conversion on ADC channel 1 will generate an interrupt.
Completion of a conversion on ADC channel 2 will not generate an interrupt.
Completion of a conversion on ADC channel 2 will generate an interrupt.
. It is important to use one method consistently because the DONE and
. Zero in the field indicates that the voltage on the input pin was less than,
All information provided in this document is subject to legal disclaimers.
s, potentially causing erroneous interrupts or DMA activity.
Rev. 2 — 19 August 2010
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
REFN
, while 0xFFF indicates that the voltage on the
REFP
.
A/D Channel Data
REFP
UM10360
© NXP B.V. 2010. All rights reserved.
to
Reset
value
0
0
0
A/D
Reset
value
NA
NA
NA
NA
NA
0
0
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