LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 57

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Table 41.
Table 42.
Bit
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
27:26
29:28
31:30
PCLKSEL0 and PCLKSEL1
individual peripheral’s clock
select options
00
01
10
11
Symbol
PCLK_QEI
PCLK_GPIOINT
PCLK_PCB
PCLK_I2C1
-
PCLK_SSP0
PCLK_TIMER2
PCLK_TIMER3
PCLK_UART2
PCLK_UART3
PCLK_I2C2
PCLK_I2S
-
PCLK_RIT
PCLK_SYSCON
PCLK_MC
Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit
description
Peripheral Clock Selection register bit values
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Description
Peripheral clock selection for the Quadrature Encoder
Interface.
Peripheral clock selection for GPIO interrupts.
Peripheral clock selection for the Pin Connect block.
Peripheral clock selection for I
Reserved.
Peripheral clock selection for SSP0.
Peripheral clock selection for TIMER2.
Peripheral clock selection for TIMER3.
Peripheral clock selection for UART2.
Peripheral clock selection for UART3.
Reserved.
Peripheral clock selection for the System Control block.
Peripheral clock selection for the Motor Control PWM.
Peripheral clock selection for I
Peripheral clock selection for I
Peripheral clock selection for Repetitive Interrupt Timer.
Function
PCLK_peripheral = CCLK/4
PCLK_peripheral = CCLK
PCLK_peripheral = CCLK/2
PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and
CAN filtering when “11” selects = CCLK/6.
Chapter 4: LPC17xx Clocking and power control
2
2
2
C1.
C2.
S.
UM10360
© NXP B.V. 2010. All rights reserved.
57 of 840
Reset
value
00
00
00
00
NA
00
00
00
00
00
00
00
NA
00
00
00
Reset
value
00