LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 513
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
24.5 Pin description
UM10360
User manual
24.4.1 Rules for Single Edge Controlled PWM Outputs
24.4.2 Rules for Double Edge Controlled PWM Outputs
Five rules are used to determine the next value of a PWM output when a new cycle is
about to begin:
Table 444
Table 444. Pin summary
Pin
PWM1[1]
PWM1[2]
PWM1[3]
PWM1[4]
PWM1[5]
PWM1[6]
PCAP1[1:0]
1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle
2. Each PWM output will go low when its match value is reached. If no match occurs (i.e.
1. The match values for the next PWM cycle are used at the end of a PWM cycle (a time
2. A match value equal to 0 or the current PWM rate (the same as the Match channel 0
3. When match values are changing, if one of the "old" match values is equal to the
4. If both a set and a clear of a PWM output are requested at the same time, clear takes
5. If a match value is out of range (i.e. greater than the PWM rate value), no match event
unless their match value is equal to 0.
the match value is greater than the PWM rate), the PWM output remains continuously
high.
point which is coincident with the beginning of the next PWM cycle), except as noted
in rule 3.
value) have the same effect, except as noted in rule 3. For example, a request for a
falling edge at the beginning of the PWM cycle has the same effect as a request for a
falling edge at the end of a PWM cycle.
PWM rate, it is used again once if the neither of the new match values are equal to 0
or the PWM rate, and there was no old match value equal to 0.
precedence. This can occur when the set and clear match values are the same as in,
or when the set or clear value equals 0 and the other value equals the PWM rate.
occurs and that match channel has no effect on the output. This means that the PWM
output will remain always in one state, allowing always low, always high, or
"no change" outputs.
gives a brief summary of each of PWM related pins.
Input
Type
Output
Output
Output
Output
Output
Output
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Description
Output from PWM channel 1.
Output from PWM channel 2.
Output from PWM channel 3.
Output from PWM channel 4.
Output from PWM channel 5.
Output from PWM channel 6.
Capture Inputs. A transition on a capture pin can be configured to load
the corresponding Capture Register with the value of the Timer
Counter and optionally generate an interrupt. The PWM brings out 2
capture inputs.
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
UM10360
© NXP B.V. 2010. All rights reserved.
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