LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 35

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
4.5 PLL0 (Phase Locked Loop 0)
UM10360
User manual
4.5.1.1 PLL0 and startup/boot code interaction
4.5.1 PLL0 operation
PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock
source is selected in the CLKSRCSEL register (see
multiplied up to a high frequency, then divided down to provide the actual clock used by
the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem
has its own dedicated PLL (see
maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and
LPC1759), and 100 MHz on other versions.
The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the
range of 6 through 512, plus additional values listed in
must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO
output by the value of M, then using a phase-frequency detector to compare the divided
CCO output to the multiplier input. The error value is used to adjust the CCO frequency.
There are additional dividers at the output of PLL0 to bring the frequency down to what is
needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output
dividers are described in the Clock Dividers section following the PLL0 description. A
block diagram of PLL0 is shown in
PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values
are controlled by the PLL0CFG register. These two registers are protected in order to
prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip
operations, including the Watchdog Timer, could be dependent on PLL0 if so configured
(for example when it is providing the chip clock), accidental changes to the PLL0 setup
values could result in unexpected or fatal behavior of the microcontroller. The protection is
accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL0FEED register.
PLL0 is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL0 must be configured, enabled, and connected to the system by software.
It is important that the setup procedure described in
sequence”
When there is no valid user code (determined by the checksum word) in the user flash or
the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the
boot code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is
disabled when the user opens a debug session to debug the application code. The user
startup code must follow the steps described in this chapter to disconnect the PLL.
is followed or PLL0 might not operate at all!
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section
Figure 9
Chapter 4: LPC17xx Clocking and power control
4.6). PLL0 can produce a clock up to the
Section
Section 4.5.13 “PLL0 setup
Table
4.4). The input frequency is
21. The resulting frequency
UM10360
© NXP B.V. 2010. All rights reserved.
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