LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 45

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Example 3
Assumptions:
Calculations:
M = (F
The smallest integer multiple of the desired CPU clock rate that is within the PLL0
operating range is 288 MHz (4 × 72 MHz).
Using the equation above and assuming that N = 1, M = ((288 × 10
4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with
this setting. Since this example is less obvious, it may be useful to make a table of
possibilities for different values of N (see below).
Table 28.
Beyond N = 5, the value of M is out of range or not supported, so the table stops at that
point. In the third column of the table, the calculated M value is rounded to the nearest
integer. If this results in CCLK being above the maximum operating frequency, it is
allowed if it is not more than 1/2 % above the maximum frequency.
In general, larger values of F
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm. There are no allowed combinations
that give a smaller error than that.
Remember that when a frequency below about 1 MHz is used as the PLL0 clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 28
calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit.
The value written to PLL0CFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section
N
1
2
3
4
5
•
•
•
The USB interface will not be used in the application, or will be clocked by PLL1.
The desired CPU rate is 72 MHz
The 32.768 kHz RTC clock source will be used as the system clock source
M
4394.53125
8789.0625
13183.59375
17578.125
21972.65625
CCO
4.7.1.
of this example are supported, which may be confirmed in
Potential values for PLL example
× N) / (2 × F
All information provided in this document is subject to legal disclaimers.
M Rounded
4395
8789
13184
17578
21973
Rev. 2 — 19 August 2010
IN
)
REF
result in a more stable PLL when the input clock is a low
F
(F
32768
16384
10922.67
8192
6553.6
REF
IN
Chapter 4: LPC17xx Clocking and power control
/ N)
in Hz
F
(F
288.0307
287.9980
288.0089
287.9980
288.0045
CCO
REF
in MHz
x M)
CCLK in MHz
(F
72.0077
71.9995
72.0022
71.9995
72.0011
CCO
/ 4)
6
) × 1) / (2 × 32,768) =
Table
UM10360
© NXP B.V. 2010. All rights reserved.
26. If PLL0
% Error
(CCLK-72) / 72
0.0107
-0.0007
0.0031
-0.0007
0.0016
45 of 840