LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 285

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 266. I
UM10360
User manual
Bit
6
7
8
31:9 -
Symbol
RFDAIE
TFFIE
SRST
2
13.8.14 I
13.8.15 I
13.8.16 Interrupt handling
C Control register (I2C_CTL - address 0x5000 C308) bit description
Value Description
0
1
0
1
0
1
NA
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
high period of the slower I
Table 267. I
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
low period of the slower I
Table 268. I
The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All
OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt
register.
Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that
data is available in the receive FIFO (i.e. not empty).
Disable the DAI.
Enable the DAI.
Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt
to indicate that the more data can be written to the transmit FIFO. Note that this is not full.
It is intended help the CPU to write to the I
and do this without polling the status register.
Disable the TFFI.
Enable the TFFI.
Soft reset. This is only needed in unusual circumstances. If a device issues a start
condition without issuing a stop condition. A system timer may be used to reset the I
the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx
FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset
to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are
NOT modified by a soft reset.
See the text.
Reset the I
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Bit
7:0
Bit
7:0
2
2
C Clock High Register (I2C_CLKHI - 0x5000 C30C)
C Clock Low Register (I2C_CLKLO - 0x5000 C310)
Symbol
CDHI
Symbol
CDLO
2
C to idle state. Self clearing.
2
2
C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description
C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
2
2
C serial clock, SCL.
C serial clock, SCL.
Description
Clock divisor high. This value is the number of 48 MHz
clocks the serial clock (SCL) will be high.
Description
Clock divisor low. This value is the number of 48 MHz
clocks the serial clock (SCL) will be low.
2
C block only when there is room in the FIFO
Chapter 13: LPC17xx USB OTG
UM10360
© NXP B.V. 2010. All rights reserved.
2
C if
285 of 840
Reset
Value
0
0
0
NA
Reset
Value
0xB9
Reset
Value
0xB9