LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 43

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
4.5.12 Examples of PLL0 settings
The following table gives a summary of examples that illustrate selecting PLL0 values
based on different system requirements.
Table 27.
Example 1
Assumptions:
Calculations:
M = (F
A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M),
both result in better PLL operational stability and lower output jitter. Lower values of F
also save power. So, the process of determining PLL setup parameters involves looking
for the smallest N and M values giving the lowest F
CPU and/or USB clocks. It is usually easier to work backward from the desired output
clock rate and determine a target F
the available input clock.
Potential precise values of F
example, it is clear that the smallest frequency for F
clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz
(3 × 100 MHz).
Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives
M = ((300 × 10
no need to look any further for a good set of PLL0 configuration values. The value written
to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section
Example
•
•
•
The USB interface will not be used in the application, or will be clocked by PLL1.
The desired CPU rate is 100 MHz.
An external 10 MHz crystal or clock source will be used as the system clock source.
1
2
3
CCO
4.7.1.
Summary of PLL0 examples
× N) / (2 × F
Description
• The PLL0 clock source is 10 MHz.
• PLL0 is not used as the USB clock source, or the USB interface is not used.
• The desired CPU clock is 100 MHz.
• The PLL0 clock source is 4 MHz.
• PLL0 is used as the USB clock source.
• The desired CPU clock is 60 MHz.
• The PLL0 clock source is the 32.768 kHz RTC clock.
• PLL0 is not used as the USB clock source, or the USB interface is not used.
• The desired CPU clock is 72 MHz.
6
All information provided in this document is subject to legal disclaimers.
× 1) / (2 × 10 × 10
Rev. 2 — 19 August 2010
IN
)
CCO
are integer multiples of the desired CPU clock. In this
6
CCO
) = 300 / 20 = 15. Since the result is an integer, there is
Chapter 4: LPC17xx Clocking and power control
rate, then find a way to obtain that F
CCO
CCO
value that will support the required
that can produce the desired CPU
UM10360
© NXP B.V. 2010. All rights reserved.
CCO
rate from
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CCO