LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 431

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
19.6 I
UM10360
User manual
2
C operating modes
19.6.1 Master Transmitter mode
Any of the I
I/O pins. These pins also support I
primary difference is that these pins do not include an analog spike suppression filter that
exists on the specialized I
serve the same purpose.
In a given application, the I
mode, the I
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I
immediately and can detect any of its own configured slave addresses in the same serial
transfer.
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the I2CONSET register must be initialized as shown in
must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI bit is cleared by writing 1 to the
SIC bit in the I2CONCLR register. THe STA bit should be cleared after writing the slave
address.
Table 381. I2C0CONSET and I2C1CONSET used to configure Master mode
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I
I
condition is transmitted, the SI bit is set, and the status code in the I2STAT register is
0x08. This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by
writing a 1 to the SIC bit in the I2CONCLR register.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in
2
Bit
Symbol
Value
C logic will send the START condition as soon as the bus is free. After the START
2
C interface will enter master transmitter mode when software sets the STA bit. The
7
-
-
2
2
C hardware looks for any one of its four slave addresses and the General Call
C interfaces brought out to pins other than those just mentioned use standard
Table 398
All information provided in this document is subject to legal disclaimers.
6
I2EN
1
Rev. 2 — 19 August 2010
to
2
2
Table
C pads. The I
C block may operate as a master, a slave, or both. In the slave
5
STA
0
2
C function. If the AA bit is 0, the I
401.
2
C operation in fast mode and standard mode. The
2
4
STO
0
C interfaces all include a digital filter that can
2
C block switches to the slave mode
3
SI
0
Chapter 19: LPC17xx I2C0/1/2
2
AA
0
2
C interface will not
UM10360
1
-
-
© NXP B.V. 2010. All rights reserved.
Table
381. I2EN
0
-
-
431 of 840