LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 794

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.5.8.2 Updating an MPU region using multi-word writes
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
STR R1, [R0, #0x0]
BIC R2, R2, #1
STRH R2, [R0, #0x8]
STR R4, [R0, #0x4]
STRH R3, [R0, #0xA]
ORR R2, #1
STRH R2, [R0, #0x8]
Software must use memory barrier instructions:
However, memory barrier instructions are not required if the MPU setup process starts by
entering an exception handler, or is followed by an exception return, because the
exception entry and exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it
accesses the MPU through the PPB, which is a Strongly-Ordered memory region.
For example, if you want all of the memory access behavior to take effect immediately
after the programming sequence, use a DSB instruction and an ISB instruction. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is
required if the code that programs the MPU region or regions is entered using a branch or
call. If the programming sequence is entered using a return from exception, or by taking
an exception, then you do not require an ISB.
You can program directly using multi-word writes, depending on how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
•
•
before MPU setup if there might be outstanding memory transfers, such as buffered
writes, that might be affected by the change in MPU settings
after MPU setup if it includes memory transfers that must use the new MPU settings.
All information provided in this document is subject to legal disclaimers.
; 0xE000ED98, MPU region number register
Rev. 2 — 19 August 2010
; 0xE000ED98, MPU region number register
; Region Number
; Disable
; Region Size and Enable
; Region Base Address
; Region Attribute
; Enable
; Region Size and Enable
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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