DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 116

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4
5.4.1
There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore
the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features.
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should
be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in
the interrupt handling routine and clear the IRQnF bit (n = 0 to 7) in ISR to 0. Interrupts may not
be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
Rev.2.00 May. 28, 2009 Page 76 of 732
REJ09B0059-0200
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
by software.
Interrupt Sources
External Interrupt Sources