DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 20

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Serial Communication Interface (SCI) ............................................445
16.1 Features............................................................................................................................. 445
16.2 Input/Output Pins .............................................................................................................. 447
16.3 Register Descriptions ........................................................................................................ 448
16.4 Operation in Asynchronous Mode .................................................................................... 462
16.5 Multiprocessor Communication Function......................................................................... 473
16.6 Operation in Clocked Synchronous Mode ........................................................................ 479
16.7 Interrupt Sources............................................................................................................... 488
16.8 Usage Notes ...................................................................................................................... 490
Rev.2.00 May. 28, 2009 Page xviii of xxxviii
REJ09B0059-0200
15.5.3 Changing Values of CKS2 to CKS0 Bits............................................................. 443
15.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 443
16.3.1 Receive Shift Register (RSR) .............................................................................. 448
16.3.2 Receive Data Register (RDR) .............................................................................. 448
16.3.3 Transmit Data Register (TDR)............................................................................. 448
16.3.4 Transmit Shift Register (TSR) ............................................................................. 449
16.3.5 Serial Mode Register (SMR) ............................................................................... 449
16.3.6 Serial Control Register (SCR).............................................................................. 451
16.3.7 Serial Status Register (SSR) ................................................................................ 453
16.3.8 Serial Interface Mode Register (SCMR).............................................................. 455
16.3.9 Bit Rate Register (BRR) ...................................................................................... 456
16.4.1 Data Transfer Format........................................................................................... 463
16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous
16.4.3 Clock.................................................................................................................... 465
16.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 466
16.4.5 Serial Data Transmission (Asynchronous Mode) ................................................ 467
16.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 469
16.5.1 Multiprocessor Serial Data Transmission ............................................................ 475
16.5.2 Multiprocessor Serial Data Reception ................................................................. 476
16.6.1 Clock.................................................................................................................... 479
16.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 480
16.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 481
16.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 484
16.6.5 Simultaneous Serial Data Transmission and Reception
16.8.1 Module Stop Mode Setting .................................................................................. 490
16.8.2 Break Detection and Processing .......................................................................... 490
16.8.3 Mark State and Break Sending............................................................................. 490
16.8.4 Receive Error Flags and Transmit Operations
16.8.5 Relation between Writing to TDR and TDRE Flag ............................................. 490
Mode .................................................................................................................... 464
(Clocked Synchronous Mode) ............................................................................. 486
(Clocked Synchronous Mode Only) .................................................................... 490