DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 291
![IC H8S/2437 MCU FLASH 128QFP](/photos/12/29/122945/df2437fv_sml.jpg)
DF2437FV
Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of DF2437FV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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For example, if an input capture occurs when ICRA is specified as the input capture register and
ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then
transferred to the buffer register ICRC. In this case, setting the IEDGA and IEDGC bits in TCR to
the different values enables the rising- or falling-edge sensing to be specified.
To ensure input capture, the input capture pulse width should be at least 1.5 system clocks (φ) for
a single edge. When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clocks (φ).
ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is
initialized to H'0000.
10.3.4
OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is
set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The
contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is
written to OCRA. The write operation is performed on the occurrence of compare-match A.
In the first compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation
due to compare-match A varies according to whether the compare-match follows addition of
OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a
compare-match A following addition of OCRAF, while 0 is output on a compare-match A
following addition of OCRAR.
When using the OCRA automatic addition function, do not select internal clock φ/2 as the FRC
input clock together with a set value of H'0001 or less for OCRAR (or OCRAF).
OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units.
OCRAR and OCRAF are initialized to H'FFFF.
10.3.5
OCRDM is a 16-bit readable/writable register in which the upper eight bits are fixed to H'00.
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to
the contents of ICRD, and the result is compared with the FRC value. The point at which the
values match is taken as the end of the mask interval. New input capture D events are disabled
during the mask interval. A mask interval is not generated when the contents of OCRDM are
H'0000 while the ICRDMS bit is set to 1.
Output Compare Registers AR and AF (OCRAR and OCRAF)
Output Compare Register DM (OCRDM)
Rev.2.00 May. 28, 2009 Page 251 of 732
REJ09B0059-0200
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