DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 358

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 12.7 TPSC2 to TPSC0 (Channel 2)
Note: This setting is ignored when channel 2 is in phase counting mode.
12.3.2
TMDR sets the operating mode for each channel. The TPU has a total of three TMDR registers,
one for each channel. TMDR settings should be made only when TCNT operation is stopped.
Rev.2.00 May. 28, 2009 Page 318 of 732
REJ09B0059-0200
Channel
2
Bit
7, 6
5
Bit Name
—
BFB
Timer Mode Register (TMDR)
Bit 2
TPSC2
0
1
Initial Value R/W
All 1
0
Bit 1
TPSC1
0
1
0
1
—
R/W
Description
Reserved
These bits are always read as 1 and cannot be modified.
Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register,
TGRD input capture/output compare is not generated. In
channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Bit 0
TPSC0
0
1
0
1
0
1
0
1
Description
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/1024