DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 454

IC H8S/2437 MCU FLASH 128QFP

DF2437FV

Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of DF2437FV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.4.7
With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IHI signal source and the waveform required by an external
circuitry. The HSYNCO output modes are shown in table 13.11.
Table 13.11 HSYNCO Output Modes
Rev.2.00 May. 28, 2009 Page 414 of 732
REJ09B0059-0200
Mode
No signal
S-on-G mode
Composite
mode
Separate
mode
HSYNCO Output
IHI Signal
HFBACKI
input
CSYNCI
input
HSYNCI
input
HSYNCI
input
IHO Signal
IHI signal (without
2fH modification)
IHI signal (with
2fH modification)
CL1 signal
IHG signal
IHI signal (without
2fH modification)
IHI signal (with
2fH modification)
CL1 signal
IHG signal
IHI signal (without
2fH modification)
IHI signal (with
2fH modification)
CL1 signal
IHG signal
IHI signal (without
2fH modification)
IHI signal (with
2fH modification)
CL1 signal
IHG signal
Meaning of IHO Signal
HFBACKI input is output directly
Meaningless unless there is a double-frequency
part in the HFBACKI input
1 interval of HFBACKI input is changed before
output
Internal synchronization signal is output
CSYNCI input (composite synchronization
signal) is output directly
Double-frequency part of CSYNCI input
(composite synchronization signal) is eliminated
before output
Horizontal synchronization signal part of
CSYNCI input (composite synchronization
signal) is separated before output
Internal synchronization signal is output
HSYNCI input (composite synchronization
signal) is output directly
Double-frequency part of HSYNCI input
(composite synchronization signal) is eliminated
before output
Horizontal synchronization signal part of
HSYNCI input (composite synchronization
signal) is separated before output
Internal synchronization signal is output
HSYNCI input (horizontal synchronization signal)
is output directly
Meaningless unless there is a double-frequency
part in the HSYNCI input (horizontal
synchronization signal)
1 interval of HSYNCI input (horizontal
synchronization signal) is changed before output
Internal synchronization signal is output

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