DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 27

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 9.4
Figure 9.5
Figure 9.6
Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10 Buffered Input Capture Timing (BUFEA = 1).....................................................264
Figure 10.11 Timing of Input Capture Flags (ICFA to ICFD) Setting......................................264
Figure 10.12 Timing of Output Compare Flag (OCFA or OCFB) Setting................................265
Figure 10.13 Timing of OVF Flag Setting ................................................................................266
Figure 10.14 OCRA Automatic Addition Timing.....................................................................266
Figure 10.15 Timing of Input Capture Mask Signal Setting .....................................................267
Figure 10.16 Timing of Input Capture Mask Signal Clearing...................................................267
Figure 10.17 FRC Write-Clear Conflict....................................................................................269
Figure 10.18 FRC Write-Increment Conflict ............................................................................270
Figure 10.19 Conflict between OCR Write and Compare-Match
Figure 10.20 Conflict between OCRAR/OCRAF Write and Compare-Match
Section 11 8-Bit Timer (TMR)
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
Figure 11.10 Timing of OVF Flag Setting ................................................................................297
Figure 11.11 Timing of Input Capture Operation......................................................................300
Figure 11.12 Timing of Input Capture Signal
Figure 11.13 Conflict between TCNT Write and Clear ............................................................303
Output Waveform (OS = 1, DADR Corresponds to T
D/A Data Register Configuration when CFS = 1.................................................244
Output Waveform when DADR = H'0207 (OS = 1)............................................245
Block Diagram of 16-Bit Free-Running Timer....................................................248
Example of Pulse Output .....................................................................................259
Increment Timing with Internal Clock Source.....................................................260
Increment Timing with External Clock Source....................................................260
Timing of Output Compare A Output..................................................................261
Clearing of FRC by Compare-Match A Signal....................................................261
Timing of Input Capture Input Signal (Usual Case) ............................................262
Timing of Input Capture Input Signal (When ICRA to ICRD are Read).............262
Buffered Input Capture Timing............................................................................263
Block Diagram of 8-Bit Timer (TMR0 and TMR1) ............................................276
Block Diagram of 8-Bit Timer (TMRY and TMRX)...........................................277
Pulse Output Example..........................................................................................293
Count Timing for Internal Clock Input ................................................................294
Count Timing for External Clock Input ...............................................................294
Timing of CMF Setting at Compare-Match.........................................................295
Timing of Counter Clear by Compare-Match ......................................................296
Timing of Counter Clear by External Reset Input ...............................................296
(When Automatic Addition Function is not Used) ..............................................271
(When Automatic Addition Function is Used) ....................................................272
Timing of Toggled Timer Output by Compare-Match A Signal .........................295
(When Input Capture Signal is Input during TICRR and TICRF Read) ..............301
Rev.2.00 May. 28, 2009 Page xxv of xxxviii
H
) ......................................244
REJ09B0059-0200