DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 623

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• In download processing, all interrupts are not accepted. However, interrupt requests other than
• When the level-detection interrupt requests need to be retained, interrupts must be input until
• When hardware standby mode is entered during download processing, the normal download
• Since a stack area of 128 bytes at the maximum is used, the area must be saved before setting
4. Clear FKEY to H'00 for protection
5. Check the value of DPFR to confirm the download result
• Check the value of DPFR (one byte of start address of the download destination specified by
• If the value of DPFR is the same as that before downloading (e.g. H'FF), the address setting of
• If the value of DPFR is different from that before downloading, check the SS and FK bits in
6. Set the operating frequency to FPEFEQ for initialization
• The current frequency of the CPU clock is set to FPEFEQ (general register ER0).
7. Execute initialization
• The general registers other than R0L are retained in the initialization program.
the NMI are retained. Therefore, when the user procedure program is returned, the interrupts
occur.
the download is ended.
cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again.
the SCO bit to 1.
FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00,
the source that caused download to fail can be investigated by the description below.
the download destination in FTDAR may be abnormal. In this case, confirm the setting of the
TDER bit in FTDAR.
DPFR to ensure that the download program selection and FKEY setting were normal,
respectively.
The settable range of FPEFEQ is 5 to 20 MHz. When the frequency is set to out of this range,
an error is returned to FPFR of the initialization program and initialization is not performed.
For details on the frequency setting, see section 20.3.2 (2) (a), Flash Program/Erase Frequency
Parameter (FPEFEQ).
When the programming program is downloaded, the initialization program is also downloaded
to the on-chip RAM. There is an entry point of the initialization program in the area from the
start address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine should be
called and initialization should be executed by using the following steps.
MOV.L
JSR
NOP
#DLTOP+32,ER2
@ER2
; Set entry address to ER2
; Call initialization routine
Rev.2.00 May. 28, 2009 Page 583 of 732
REJ09B0059-0200