DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 693

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Exiting Sleep Mode by STBY Pin
22.2.3
Transition to Software Standby Mode:
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
However, the contents of the CPU’s internal registers, on-chip RAM data, and the states of on-
chip peripheral functions other than the PWM, PWMX, SCI, IIC3, and A/D converter, and I/O
ports, are retained. Whether the address bus and bus control signals are placed in the high-
impedance state or retain the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power consumption is significantly reduced.
Clearing Software Standby Mode:
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by
means of the RES pin or STBY pin. Setting the SSI bit in SSIER to 1 enables IRQ0 to IRQ7 to be
used as software standby mode clearing sources.
• Clearing with Interrupt
• Clearing with RES Pin
• Clearing with STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to
the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side.
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU starts reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Software Standby Mode
Rev.2.00 May. 28, 2009 Page 653 of 732
REJ09B0059-0200