DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 627

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A single divided block is erased in one erasing processing. For block divisions, see figure 20.4. To
erase two or more blocks, update the erase block number and perform the erasing processing for
each block.
1. Select the on-chip program to be downloaded
2. Set FEBS necessary for erasure
3. Execute erasing
4. Check the return value in the erasing program, FPFR (general register R0L)
5. Determine whether erasure of the necessary blocks has completed
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the SS bit in DPFR.
Specify the start address of a download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, see section 20.4.2 (2), Programming
Procedure in User Program Mode.
The procedures after setting parameters for erasing programs are as follows:
Set the erase block number of the user MAT to the flash erase block select parameter FEBS
(general register ER0). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
Similar to as in programming, there is an entry point of the erasing program in the area from
the start address of a download destination specified by FTDAR + 16 bytes of on-chip RAM.
The subroutine should be called and erasing should be executed by using the following steps.
MOV.L
JSR
NOP
•
•
•
If several blocks need to be erased, update FEBS and repeat steps 2 to 5. Blocks that have
already been erased can be erased again.
The general registers other than R0L are retained in the erasing program.
R0L is a return value of FPFR.
Since the stack area is used in the erasing program, a stack area of 128 bytes at the
maximum must be saved in RAM.
#DLTOP+16,ER2
@ER2
; Set entry address to ER2
; Call erasing routine
Rev.2.00 May. 28, 2009 Page 587 of 732
REJ09B0059-0200