DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 19

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Duty Measurement Circuit.............................................................. 417
14.1 Features .............................................................................................................................417
14.2 Input/Output Pins .............................................................................................................. 419
14.3 Register Descriptions ........................................................................................................420
14.4 Operation...........................................................................................................................424
14.5 Operation Timing..............................................................................................................425
14.6 Interrupt Sources ...............................................................................................................428
14.7 Usage Notes ......................................................................................................................429
Section 15 Watchdog Timer (WDT)................................................................. 435
15.1 Features .............................................................................................................................435
15.2 Register Descriptions ........................................................................................................437
15.3 Operation...........................................................................................................................439
15.4 Interrupt Sources ...............................................................................................................441
15.5 Usage Notes ......................................................................................................................442
13.4.7 HSYNCO Output .................................................................................................414
13.4.8 VSYNCO Output .................................................................................................415
13.4.9 CBLANK Output .................................................................................................416
14.3.1 Free-Running Counter (TWCNT)........................................................................420
14.3.2 Input Capture Register (TWICR).........................................................................420
14.3.3 Duty Measurement Control Register 1 (TWCR1) ...............................................421
14.3.4 Duty Measurement Control Register 2 (TWCR2) ...............................................422
14.4.1 Duty Measurement for External Event Signal .....................................................424
14.5.1 TWCNT Count Timing........................................................................................425
14.5.2 TWCNT Clear Timing by Setting START Bit ....................................................425
14.5.3 Count Start Timing for Duty Measurement .........................................................426
14.5.4 Capture Timing during Duty Measurement .........................................................426
14.5.5 Clear Timing for START Bit when Duty Measurement Ends .............................427
14.5.6 Set Timing for Duty Measurement End Flag (ENDF) .........................................427
14.5.7 Set Timing for Overflow Flag (OVF) ..................................................................428
14.7.1 Conflict between TWCNT Write and Increment .................................................429
14.7.2 Write to START Bit during Free-Running Counter Operation............................430
14.7.3 Switching of Internal Clock and TWCNT Operation ..........................................430
14.7.4 Switching of External Event Signal and Operation of Edge Detection Circuit....433
15.2.1 Timer Counter (TCNT)........................................................................................437
15.2.2 Timer Control/Status Register (TCSR) ................................................................437
15.3.1 Watchdog Timer Mode ........................................................................................439
15.3.2 Interval Timer Mode ............................................................................................440
15.3.3 Internal Reset Signal Generation Timing.............................................................441
15.5.1 Notes on Register Access.....................................................................................442
15.5.2 Conflict between Timer Counter (TCNT) Write and Increment..........................443
Rev.2.00 May. 28, 2009 Page xvii of xxxviii
REJ09B0059-0200