DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 426

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 May. 28, 2009 Page 386 of 732
REJ09B0059-0200
Bit
4
3
2
Bit Name
ICST
HFINV
VFINV
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Input Capture Start Bit
The TMRX external reset input (TMRIX) is
connected to the IHI signal. The TMRX has input
capture registers (TICR, TICRR, and TICRF). TICRR
and TICRF can measure the width of a short pulse
by means of a single capture operation under the
control of the ICST bit. When a rising edge followed
by a falling edge is detected on the TMRIX after the
ICST bit is set to 1, the contents of TCNT at those
points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
0: Input capture function of TICRR and TICRF is
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
1: Input capture function of TICRR and TICRF is
[Setting condition]
When 1 is written to ICST after reading ICST = 0
Spare Horizontal Synchronization Signal Inversion
Selects inversion of the input phase of the spare
horizontal synchronization signal (HFBACKI). This
bit is reserved in channel 1. The initial value should
not be changed.
0: The HFBACKI pin state is used directly as the
1: The HFBACKI pin state is inverted before use as
Spare Vertical Synchronization Signal Inversion
Selects inversion of the input phase of the spare
vertical synchronization signal (VFBACKI). This bit is
reserved in channel 1. The initial value should not be
changed.
0: The VFBACKI pin state is used directly as the
1: The VFBACKI pin state is inverted before use as
halted
operating (Waiting for the time when a rising edge
followed by a falling edge is detected on TMRIX)
HFBACKI input
the HFBACKI input
VFBACKI input
the VFBACKI input