DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 140

IC H8S/2437 MCU FLASH 128QFP

DF2437FV

Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of DF2437FV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 6.3
[Legend]
n = 1 to 3
*: Don’t care.
Multiplex Extended Mode:
The bus access is used as both the address bus and the data bus, but not simultaneously.
1. Bus Width
2. Number of Access States
3. Wait Mode and Number of Program Wait States
Rev.2.00 May. 28, 2009 Page 100 of 732
REJ09B0059-0200
ASTn
0
1
A bus width of 8 or 16 bits can be selected with the ABWn bit in BCRAn. The bus width of
the address cycle and the data cycle are the same.
⎯ Address cycle state
⎯ Data cycle state
⎯ Address cycle wait
⎯ Data cycle wait
The address cycle state is 2-state.
The number of access states for data access , 2-state or 3-state can be selected with the
ASTn bit in BCRAn. When 2-state access space is designated, wait state insertion is
disabled.
The number of program wait states to be inserted into the address cycle are selected by the
AWn bit in BCRAn. 0 or 1 address cycle program wait states can be selected. The address
cycle wait is not affected by the number of data access wait states or the wait mode.
When 3-state access space is designated by the ASTn bit in BCRAn, the number of
program wait states to be inserted automatically are selected with WMSn1, WMSn0,
WCn1, and WCn0 in the BCRAn. From 0 to 3 data cycle wait states can be selected.
Bus Specifications for Normal Extended Bus Interface
WMSn1
0
0
1
WMSn0
1
0
*
WCn1
0
1
WCn0
0
1
0
1
Number of
Access
States
2
3
3
3
3
3
Number of
Program
Wait States
0
0
0
1
2
3

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